Common-gate circuit

The common-gate circuit (Fig. 1) has the gate at signal ground. The input is applied to the source. The illustration shows an N-channel JFET. For other types of FETs, the same considerations apply as described above for the common-source circuit. Enhancement-mode devices would require a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel).

Fig. 1: Common-gate circuit configuration.

The dc bias for the common-gate circuit is basically the same as that for the common- source arrangement. But the signal follows a different path. The ac input signal enters through C1. Resistor R1 keeps the input from being shorted to ground. Gate bias is provided by R1 and R2; capacitor C2 places the gate at signal ground. In some common- gate circuits, the gate electrode is directly grounded, and components R2 and C2 are not used. The output leaves the circuit through C3. Resistor R3 keeps the output signal from being shorted through the power supply.
The common-gate arrangement produces less gain than its common-source counterpart. But this is not all bad; a common-gate amplifier is very stable, and is not likely to break into unwanted oscillation. The output is in phase with the input.

مواضيع ذات صلة

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الحساسات النانوية للحالة الصلبة

الحساسات النانوية لرصد ملوثات الهواء

تكنولوجيا النانو وصناعة الحساسات

الحساسات النانوية

تقنية النانو في الطباعة على الأسطح Nano–Lithography

تقنية الطباعة على الأسطح Lithography

التنافس العالمي في إنتاج الحاسبات المعتمدة على تكنولوجيا النانو

قانون مور

تركيب الترانزستور وكيفية عمله

ماهية الترانزستورات