Voltage amplification

The graph of Fig. 1 shows the drain (channel) current, I_D, as a function of the gate bias voltage, E_G, for a hypothetical N-channel JFET. The drain voltage, E_D, is assumed to be constant.

Fig. 1 Relative drain current as a function of gate voltage for a hypothetical N-channel JFET.

When E_G is fairly large and negative, the JFET is pinched off, and no current flows through the channel. As E_G gets less negative, the channel opens up, and current begins flowing. As E_G gets still less negative, the channel gets wider and the current I_D increases. As E_G approaches the point where the SG junction is at forward breakover, the channel conducts as well as it possibly can.
If E_G becomes positive enough so that the SG junction conducts, the JFET will no longer work properly. Some of the current in the channel will then be shunted off through the gate, a situation that is never desired in a JFET. The hose will spring a leak!
The best amplification for weak signals is obtained when the gate bias, E_G, is such that the slope of the curve in Fig. 1 is the greatest. This is shown roughly by the range marked X in the figure. For power amplification, however, results are often best when the JFET is biased at, or even beyond, pinchoff, in the range marked Y.
The current I_D passes through the drain resistor. Small fluctuations in E_G cause large changes in I_D, and these variations in turn produce wide swings in the dc voltage across R3 (at A) or R4 (at B). The ac part of this voltage goes through capacitor C2, and appears at the output as a signal of much greater ac voltage than that of the input signal at the gate. That’s voltage amplification.

مواضيع ذات صلة

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الحساسات النانوية للحالة الصلبة

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تكنولوجيا النانو وصناعة الحساسات

الحساسات النانوية

تقنية النانو في الطباعة على الأسطح Nano–Lithography

تقنية الطباعة على الأسطح Lithography

التنافس العالمي في إنتاج الحاسبات المعتمدة على تكنولوجيا النانو

قانون مور

تركيب الترانزستور وكيفية عمله

ماهية الترانزستورات